Exact Functional Fault Collapsing in Combinational Logic Circuits

Fault equivalence is an essential concept in digital VLSI design with significance in many different areas such as diagnosis, diagnostic ATPG, testability analysis and synthesis. In this paper, an efficient procedure to compute exact fault equivalence classes of combinational circuits is described. The procedure consists of two steps. The first step performs structural fault collapsing and uses fault simulation to return an approximation of the fault equivalent classes. The second step refines these classes with ATPG. Experiments on ISCAS’85 and fullscan ISCAS’89 circuits demonstrate its efficiency. Robert Chang, Sep Seyedi, Andreas Veneris Magdy S. Abadir University of Toronto Motorola Dept ECE 7700 W. Parmer Toronto, ON M5S 3G4 Austin, TX 78729 {rchang, sep, veneris} @eecg.toronto.edu [email protected]